1. Field of the Invention
The invention generally relates to communication in computer systems. More specifically the invention relates to a system having increased Peripheral Component Interconnect Express (PCIe) bandwidth.
2. Description of the Related Art
In some computer systems, a chipset communicates with one or more endpoint devices through a PCIe link. FIG. 1 is a block diagram showing a prior art computer system 100 employing PCIe links. Computer system 100 includes endpoint device 102, chipset 104, central processing unit (CPU) 106, and system memory 108. Further, chipset 104 includes a system controller 110 (e.g., a controller commonly known as northbridge) and an I/O controller 112 (e.g., a controller commonly known as southbridge). System controller 110 communicates with CPU 106, system memory 108, I/O controller 112, and endpoint device 102, which may be a graphics processing unit (GPU). I/O controller 112 communicates with system controller 110 and one or more I/O devices (not shown).
System controller 110 includes PCIe interface 114 that is used to communicate with endpoint device 102, and endpoint device 102 includes a PCIe interface 116 that is used to communicate with system controller 110. PCIe interface 114 and PCIe interface 116 are connected to each other through a PCIe link, i.e., a plurality of PCIe lanes, typically 16. Endpoint device 102 communicates with CPU 106 and system memory 108 through system controller 110. Endpoint device 102 communicates with I/O devices connected to I/O controller 112 through system controller 110 and I/O controller 112. I/O controller 112 includes a plurality of expansion PCIe interfaces that are used for communication with I/O devices. Three of the expansion PCIe interfaces of I/O controller 112 are shown in FIG. 1. They are PCIe interface 118, PCIe interface 120, and PCIe interface 122.
In the prior art computer system 100 described above, the PCIe bandwidth available to endpoint device 102 is limited. For graphics applications that employ turbo cache technology, where part of the frame buffer resides in system memory 108, PCIe bandwidth available to endpoint device 102 is becoming the bottleneck. Optimizing the bus utilization of the PCIe link can increase the PCIe bus throughput efficiency, but the efficiency can be increased only up to a certain limit.
There is therefore, a need for a system that can increase the PCIe bandwidth available to a PCIe endpoint device.